| 摘要 |
PROBLEM TO BE SOLVED: To achieve a semiconductor device having a vertical JFET excellent in off-state performance without reducing manufacturing yield.SOLUTION: A gate region GR having a square shape in a cross section along a channel width direction is formed below a source region SR by an ion implantation of an impurity. Then, the source region SR located on a top face of the gate region GR is removed by a first etching to separate the source region SR and the gate region GR. The top face of the gate region GR is processed by a second etching in which an etching rate of a lateral face of the gate region GR is slower than that of the center of the gate region GR. Accordingly, the gate region GR including an undersurface formed in parallel with a surface of a substrate SUB, and a top face which is located below a boundary between a source region SR and a channel formation region and has inclination in a cross section along the channel width direction, which becomes lower with the distance from the lateral face toward the center, is formed to achieve a channel length with less variation. |
