| 主权项 |
1. A small form factor high performance computing platform, comprising:
a plurality of computational nodes, each computational node comprising a multi-core processor, a memory comprising a shared portion and a plurality of local memory segments associated with each of the computational nodes; a network-on-chip operable to provide data communication within the platform and comprising a low-latency mesh having first, second, and third interlocking structures and wherein on-chip write traffic of the data communication is allocated to the first interlocking structure, off-chip write traffic within the platform is allocated to the second interlocking structure, and on-chip and off-chip read within the platform traffic is allocated to the third interlocking structure; and an off-chip input-output interface operable to facilitate communications with an external component. |
