发明名称 Method of Fabricating A Variable Reistance Memory Device
摘要 A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
申请公布号 US2015104921(A1) 申请公布日期 2015.04.16
申请号 US201414318767 申请日期 2014.06.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Terai Masayuki;Baek In-Gyu
分类号 H01L45/00 主分类号 H01L45/00
代理机构 代理人
主权项 1. A method of fabricating a memory device, comprising: defining a cell region on a substrate and defining a dummy region on the substrate that surrounds the cell region; forming bit lines on a top surface of the substrate, the bit lines extending in one direction; forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element; forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element; and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles, wherein the cell diode includes a first impurity pattern that includes first conductivity type impurities and a second impurity pattern that includes second conductivity type impurities that are of an opposite conductivity type from the first conductivity type impurities, the dummy diode includes a first impurity pattern having a first concentration of the first conductivity type impurities and a second impurity pattern that includes a second concentration of the second conductivity type impurities, the first concentration being less than the second concentration, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
地址 SUWON-SI KR