PROTOCOL FOR MEMORY POWER-MODE CONTROL

摘要

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

主权项

1. A method of controlling a memory device that includes a memory core, the method comprising:
providing a self-refresh command to the memory device; and after providing the self-refresh command, providing a control signal to the memory device, wherein, in response to the self-refresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.