Package level power state optimization

摘要

Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

主权项

1. A processor comprising:
a cache; and a control logic, coupled to the cache, to receive a request to enter a lower power consumption state, wherein the control logic is to determine a time difference between a last entry into the lower power consumption state and a current time, and wherein the control logic is to cause a flush of the cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state.