发明名称 Memory device with a logical-to-physical bank mapping cache
摘要 A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.
申请公布号 US9026747(B2) 申请公布日期 2015.05.05
申请号 US201213718773 申请日期 2012.12.18
申请人 Broadcom Corporation 发明人 Wang Weihuang;Wu Chien-Hsien;Issa Mohammad
分类号 G06F12/00;G06F13/00;G06F13/28;G06F12/08;G06F12/02;G06F12/06;G11C8/00;G11C7/10 主分类号 G06F12/00
代理机构 Fiala & Weaver P.L.L.C. 代理人 Fiala & Weaver P.L.L.C.
主权项 1. A memory device comprising: a plurality of physical memory banks; at least one cache that is configured to store a logical-to-physical bank map, the logical-to-physical bank map associating each one of a plurality of logical memory banks with a corresponding one of the plurality of physical memory banks; and control logic coupled to each of the plurality of physical memory banks and to the at least one cache, the control logic being configured to: determine whether a first incoming write operation configured to write data to a first logical memory bank in the plurality of logical memory banks is blocked by at least one incoming read operation;write data associated with the first incoming write operation to a first physical memory bank that is associated with the first logical memory bank in the logical-to-physical bank map in response to determining that the first incoming write operation is not blocked by the at least one incoming read operation; andwrite data associated with the first incoming write operation to a second physical memory bank that is not associated with any logical memory bank in the logical-to-physical bank map in response to determining that the first incoming write operation is blocked by the at least one incoming read operation.
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