发明名称 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
摘要 |
A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer. |
申请公布号 |
US2015170974(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
US201214355919 |
申请日期 |
2012.12.07 |
申请人 |
Xu Qiuxia;Zhu Huilong;Xu Gaobo;Zhou Huajie;Chen Dapeng |
发明人 |
Xu Qiuxia;Zhu Huilong;Xu Gaobo;Zhou Huajie;Chen Dapeng |
分类号 |
H01L21/8238;H01L21/28;H01L21/3105;H01L21/321;H01L21/324;H01L29/167;H01L21/266;H01L29/66;H01L29/51;H01L29/423;H01L29/49;H01L21/3213;H01L21/02 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
1. A method for manufacturing a semiconductor device, comprising:
defining active regions on a semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer and/or the first metal gate layer and/or the high-K gate dielectric and/or the interfacial oxide layer, to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to exposure the surface of dummy gate layer removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer. |
地址 |
Beijing CN |