发明名称 |
Cache memory with dynamic lockstep support |
摘要 |
Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments. |
申请公布号 |
US9086977(B2) |
申请公布日期 |
2015.07.21 |
申请号 |
US201113090057 |
申请日期 |
2011.04.19 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Moyer William C. |
分类号 |
G06F12/08;G06F11/16;G06F12/12 |
主分类号 |
G06F12/08 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method comprising:
operating a computational system that includes a plurality of processors each having an associated cache way- or set-partitioned into lockstep and non-lockstep partitions; dynamically transitioning between a lockstep mode of operation and a non-lockstep mode of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences; in the non-lockstep mode, satisfying at least some load hits from the lockstep partition and at least some other load hits from the non-lockstep partition; and in the lockstep mode, satisfying load hits only from the lockstep partition. |
地址 |
Austin TX US |