Random timeslot controller for enabling built-in self test module

摘要

A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

主权项

1. A method comprising:
executing a security sensitive operation at a security sensitive module of an integrated circuit die; and receiving a random value from a random value generator for randomly enabling or disabling a BIST (built-in self test) module of the integrated circuit die concurrently with executing the security operation to change power consumption of the integrated circuit die, the BIST module configured in a test mode of operation to test a portion of the integrated circuit die.