发明名称 |
SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD THEREOF |
摘要 |
A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals. |
申请公布号 |
US2015227417(A1) |
申请公布日期 |
2015.08.13 |
申请号 |
US201414282379 |
申请日期 |
2014.05.20 |
申请人 |
SK hynix Inc. |
发明人 |
KIM Jae Il |
分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor memory apparatus comprising:
an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data in response to a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals. |
地址 |
Icheon-si KR |