发明名称 半導体装置
摘要 Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.
申请公布号 JP5770068(B2) 申请公布日期 2015.08.26
申请号 JP20110245230 申请日期 2011.11.09
申请人 发明人
分类号 G11C11/404 主分类号 G11C11/404
代理机构 代理人
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