发明名称 |
High-rate reverse-order run-length-limited code |
摘要 |
A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control. |
申请公布号 |
US9136869(B2) |
申请公布日期 |
2015.09.15 |
申请号 |
US201314054586 |
申请日期 |
2013.10.15 |
申请人 |
STMicroelectronics, Inc. |
发明人 |
Ozdemir Hakan C.;Karabed Razmik;Barndt Richard;Jeong Kuhong |
分类号 |
H03M7/46;G11B20/14;H03M5/14;G11B5/09 |
主分类号 |
H03M7/46 |
代理机构 |
Seed IP Law Group PLLC |
代理人 |
Seed IP Law Group PLLC |
主权项 |
1. A computer system; comprising:
a processor; a system bus coupled to the processor and configured to facilitate the transfer of data in the form of a stream of bits; a read/write channel coupled to the system bus, the read/write channel further comprising:
a write channel, having:
a write-channel buffer configured to receive a stream of bits to be sent to a write channel;a write-channel RLL-block configured to determine a unique sequence of bits that is not present in the stream of bits and configured to combine the unique sequence of bits with the stream of bits. |
地址 |
Coppell TX US |