| 发明名称 | Memory mapping and translation for arbitrary number of memory units | ||
| 摘要 | A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU. | ||
| 申请公布号 | US9135170(B2) | 申请公布日期 | 2015.09.15 |
| 申请号 | US201213472180 | 申请日期 | 2012.05.15 |
| 申请人 | Futurewei Technologies, Inc. | 发明人 | Kumar Sailesh;Lynch William;Philip Joji;Hanna Michel |
| 分类号 | G06F12/10;G06F12/06 | 主分类号 | G06F12/10 |
| 代理机构 | Conley Rose, P.C. | 代理人 | Conley Rose, P.C. ;Rodolph Grant;Dietrich William H. |
| 主权项 | 1. A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising: determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU. | ||
| 地址 | Plano TX US | ||