发明名称 不揮発性半導体記憶装置
摘要 <p>A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block.</p>
申请公布号 JP5781109(B2) 申请公布日期 2015.09.16
申请号 JP20130040525 申请日期 2013.03.01
申请人 发明人
分类号 G11C16/02;G11C16/04 主分类号 G11C16/02
代理机构 代理人
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