| 摘要 |
Disclosed is an intermediate controller which is included in a convertor device of an HVDC system. A receiving part receives a synthesized control signal, in which a plurality of control signals corresponding to a plurality of sub modules respectively are synthesized, from a valve controller of the convertor device. A demultiplexer extracts a control signal corresponding to each sub module from the synthesized control signal. A plurality of data buses connect the sub modules and the demultiplexer to transmit the control signals, which correspond to the sub modules respectively, to each of the sub modules. |
