| 摘要 |
A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase. |
