SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE

摘要

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

主权项

1. A semiconductor device comprising a shift register,
wherein the shift register includes first to third flipflops, wherein the first flipflop has a function of outputting a first signal to a first wiring, wherein the second flipflop has a function of outputting a second signal to a second wiring, wherein the third flipflop has a function of outputting a third signal to a third wiring, wherein the first signal has a value synchronized with a first clock signal, wherein the second signal has a value synchronized with a second clock signal, wherein the third signal has a value synchronized with a third clock signal, wherein the second flipflop includes first to third transistors, wherein one of a source and a drain of the first transistor is electrically connected to a fourth wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring, wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, wherein a gate of the second transistor is electrically connected to a fifth wiring, wherein one of a source and a drain of the third transistor is electrically connected to the third wiring, wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor, wherein a gate of the third transistor is electrically connected to a sixth wiring, wherein the fourth wiring has a function of transmitting the second clock signal, wherein the fifth wiring has a function of transmitting the first clock signal, and wherein the sixth wiring has a function of transmitting the third clock signal.