DEVICE AND METHOD FOR PROCESSING IMAGES

摘要

An image processing device includes a first rearrangement circuit that receives, in parallel, pieces of line data included in image data. The first rearrangement circuit rearranges A-bit pixel data (where A is an integer that is greater than or equal to two) in the line data to arrange pixel data for only one color component in at least one of the line data. LUT correction circuits, arranged in correspondence with the line data, each include a memory that stores a lookup table and correct the rearranged A-bit pixel data using the corresponding lookup table. A second rearrangement circuit rearranges the corrected A-bit pixel data to return the A-bit pixel data rearranged by the first rearrangement circuit to an original arrangement order.

主权项

1. An image processing device comprising:
a first rearrangement circuit that receives, in parallel, plural pieces of line data included in image data, wherein the first rearrangement circuit rearranges plural pieces of A-bit pixel data (where A is an integer that is greater than or equal to two) included in the plural pieces of line data to arrange pixel data for only one color component in at least one of the plural pieces of line data; LUT correction circuits respectively arranged in correspondence with the plural pieces of line data, wherein each of the LUT correction circuits includes a memory that stores a lookup table, and each of the LUT correction circuits corrects the rearranged plural pieces of A-bit pixel data using the corresponding lookup table; and a second rearrangement circuit that rearranges the corrected plural pieces of A-bit pixel data to return the plural pieces of A-bit pixel data rearranged by the first rearrangement circuit to an original arrangement order; wherein each of the LUT correction circuits includes an LUT section that receives the corresponding one of the plural pieces of line data rearranged by the first rearrangement circuit and outputs output values from the memory using data of B upper order bits (where B is an integer that is smaller than A) of the A-bit pixel data in the received line data as an address value, and a cache memory including flip-flop circuits, each holding one of the output values; and the cache memory outputs the output value held in one of the flip-flop circuits based on data of (A-B) lower order bits of the A-bit pixel data that have been rearranged by the first rearrangement circuit.