ERROR BIT DETECTING AND CORRECTING CIRCUIT

摘要

The circuit includes a gate section (10) which consists of: first and second parity generating sections (PG1)(PG2) for generating parity bits by receiving 5-bit data; third and fourth parity generating sections (PG3)(PG4) for generating parity bits by receiving 4-bit data; and first to fourth AND gates (A0-A3) for logic-combining control signals. A parity storing section (20) includes first to fourth memories (M1-M4), and stores the outputs of the AND gates (A0-A3). Another gate section (30) includes first to fourth exclusive OR gates (B0-B3), and logic-combines the outputs of the first to fourth memories (MK1-M4) and the outputs of the first to fourth parity generating sections (PG1-PG4). A decoding section (DEC) decodes the output of the second gate section (30) to detect errors.