PROCESSOR PERFORMANCE BY DYNAMICALLY RE-ADJUSTING THE HARDWARE STREAM PREFETCHER STRIDE

摘要

An apparatus may include a first memory, a control circuit, a first address comparator and a second address comparator. The first memory may store a table, which may include an expected address of a next memory access and an offset to increment a value of the expected address. The control circuit may read data at a predicted address in a second memory and store the read data in a cache. The first and second address comparators may determine if a value of a received address is between the value of the expected address and the value of the expected address minus a value of the offset. The control circuit may also modify the value of the offset responsive to determining the value of the received address is between the value of the expected address and the value of the expected address minus the value of the offset.

主权项

1. An apparatus, comprising:
a first memory configured to store a table, wherein the table includes at least a first entry, wherein the first entry includes:
an expected address of a next memory access; andan offset to adjust a value of the expected address for a subsequent memory access; and a control circuit coupled to the first memory, wherein the control circuit is configured to:
read data at a predicted address in a second memory, wherein a value of the predicted address is dependent upon the value of the expected address and a value of the offset; andstore the read data in a cache memory; a first address comparator configured to compare a received address value of a received memory access to the value of the expected address; and a second address comparator configured to compare the received address value of the received memory access to a value dependent upon the value of the expected address and the value of the offset; wherein the control circuit is further configured to generate a new value of the offset dependent upon an output of the first comparator and an output of the second comparator.