| 摘要 |
<p>PURPOSE:To provide a semiconductor storage in which a high speed reading can be executed even in a large-scale storage cell array. CONSTITUTION:A storage cell array 11 is formed of EPROM transistors Q411-Q4mn, one cell is selected by outputs from a column decoder 13, a row decoder 14, and a cell output (a) is obtained corresponding to a first load transistor Q11. One of dummy EPROM transistors Q41-Q4m is selected corresponding to outputs of the decoders 13, 14, and a dummy cell output (b) is selected corresponding to a second load transistor Q12. The dummy cell output (b) has the same bit line capacity as that of a storage cell output, and the outputs (a) and (b) are compared by a differential amplifier 15. Thus, a reference voltage of the amplifier 15 of the output (b) is varied by following-up a variation in the output (a) of the cell.</p> |
