| 摘要 |
A p-type base region (17) in which an n + emitter region (19) is formed and a p-type floating region (16) in which the n + emitter region (19) is not formed are provided in a surface layer of one main surface of an n-type semiconductor substrate (14). The p-type base region (17) and the p-type floating region (16) are separated from each other by a trench (15). An emitter electrode (24) is provided so as to cover the p-type floating region (16), with an interlayer insulating film (25) interposed therebetween, and to come into contact with the p-type base region (17) and the n+ emitter region (19). In the trench (15), two divided polysilicon electrodes (21, 22) are provided in regions that face each other, with a cavity (26), which is surrounded by an insulating film (23), interposed therebetween, and are arranged along both side walls of the trench (15) and are connected to different electrodes. According to this structure, it is possible to ensure the insulation between the polysilicon electrodes (21, 22) in the trench (15) and to reduce stress. In addition, it is possible to suppress an increase in gate capacitance. |
