发明名称 INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES
摘要 <p>A multilevel interconnect structure (10) is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels (12) of conductors are staggered from each other (16) in separate vertical and horizontal planes. A third conductor (16) is advantageously spaced a lateral distance between at least a portion of two second conductors (26). The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.</p>
申请公布号 WO1998003994(A1) 申请公布日期 1998.01.29
申请号 US1997009452 申请日期 1997.05.27
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址