发明名称 Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks
摘要 One aspect interconnects two regions subject to different rules and using transition rule(s) in a transition region or cost mechanism(s), where these rules may include soft rule(s), hard rule(s), or combinations thereof. These two regions may reside on the same routing layer or on different routing layers. This aspect allows physical design tools to transition across gridded, gridless, tracked, or trackless regions subject to different rules on the same or different layers. Another aspect interconnects an object subject to the first rule(s) and the second rule(s), while the object satisfies or violates the first rule(s). These aspects use spacetile(s) on a spacetile layer as search probe(s) to find viable implementation solutions, although the spacetile(s) and hence the search probe may violate one or more rules. A spacetile layer may be identified or created for each rule and may be associated with relevant features subject to relevant rule(s).
申请公布号 US9213793(B1) 申请公布日期 2015.12.15
申请号 US201314044836 申请日期 2013.10.02
申请人 Cadence Design Systems, Inc. 发明人 Salowe Jeffrey S.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for implementing electronic design using flexible routing tracks, comprising: identifying, with a track pattern manipulation mechanism including or functioning in conjunction with at least one processor or at least one processor core of a computing system, a track pattern having multiple tracks and associated with a first routing rule for implementing at least a part of a net including a shape in a first region on a first layer, wherein the shape is associated with a first rule; identifying or creating one or more spacetiles based at least in part upon the shape; and implementing the at least a part of the net including the shape by using at least one spacetile of the one or more spacetiles as a search probe for implementation of the at least part of the net, wherein the at least one spacetile overlaps in part or in whole with at least the shape.
地址 San Jose CA US