发明名称 Apparatus for detecting type of audio interface
摘要 An apparatus for detecting a type of an audio interface is disclosed. The apparatus comprises: an audio interface, comprising a pin 3 and a pin 4, in which one of the pin 3 and the pin 4 is configured as a MIC pin of the audio interface, and the other one is configured as a ground pin; a first level comparison module configured to output a signal Sg1, when a level V3 of the pin 3 is greater than a sum of a level V4 of the pin 4 and a predetermined threshold Vg1, otherwise to output a signal Sg1′; a second level comparison module configured to output a signal Sg2, when the level V4 of the pin 4 is greater than a sum of the level V3 of the pin 3 and a predetermined threshold Vg2, otherwise to output a signal Sg2′.
申请公布号 US9215541(B2) 申请公布日期 2015.12.15
申请号 US201214372785 申请日期 2012.12.28
申请人 Tendyron Corporation 发明人 Li Dongsheng
分类号 H04R29/00;H04R5/04 主分类号 H04R29/00
代理机构 Lerner, David, Littenberg, Krumholz & Mentlik, LLP 代理人 Lerner, David, Littenberg, Krumholz & Mentlik, LLP
主权项 1. An apparatus for detecting a type of an audio interface, comprising: an audio interface, comprising a pin 3 and a pin 4, wherein one of the pin 3 and the pin 4 is configured as a MIC pin of the audio interface, and the other one is configured as a ground pin; a first level comparison module, connected with the pin 3 and the pin 4, and configured to output a signal Sg1 via an output end of the first level comparison module, when a level V3 of the pin 3 is greater than a sum of a level V4 of the pin 4 and a predetermined threshold Vg1, otherwise to output a signal Sg1' via the output end of the first level comparison module; a second level comparison module, connected with the pin 3 and the pin 4, and configured to output a signal Sg2 via an output end of the second level comparison module, when the level V4 of the pin is greater than a sum of the level V3 of the pin 3 and a predetermined threshold Vg2, otherwise to output a signal Sg2′ via the output end of the second level comparison module; wherein the signal Sg1 is different from the signal Sg1', the signal Sg2 is different from the signal Sg2′, and the predetermined threshold Vg1 and the predetermined threshold Vg2 are greater than or equal to 0.
地址 CN