Phase locked loop circuit

摘要

A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

主权项

1. A phase locked loop circuit comprising:
a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, and output a detection signal based on the detected phase difference; an analog-digital mixed filter configured to receive the detection signal and output a control signal based on the received detection signal; a voltage controlled oscillator configured to output an output signal based on the control signal; and a divider configured to divide the output signal by n and output the divided signal as the feedback signal, wherein the detection signal is a digital signal, and the control signal is an analog signal; and wherein the analog-digital filter includes,
a digital filter configured to filter the received detection signal to remove noise,a delta-sigma modulator configured to output first and second signals based on the filtered detection signal, andan analog integrator configured to output the control signal based on the first and second signals,wherein the analog integrator includes,
a pulse generator configured to adjust pulse widths of the first and second signals and output pull-up and pull-down signals based on the adjusted pulse widths of the first and second signals; anda charge pump array including a plurality of charge pumps and configured to output the control signal based on the pull-up and pull-down signals.