Controller to manage NAND memories

摘要

In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

主权项

1. A controller, comprising:
a protocol interface circuit to exchange signals with a host processor; and a NAND interface coupled to the protocol interface circuit to manage a plurality of NAND memory devices, the NAND interface being configured to provide power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.