Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device

摘要

One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

主权项

1. A method of forming a FinFET device, comprising:
forming a first epi semiconductor material on a semiconductor substrate; forming a second epi semiconductor material on said first epi semiconductor material; performing at least one trench etching process to define a plurality of trenches in said semiconductor substrate so as to thereby define an initial fin structure comprised of a portion of said semiconductor substrate, a portion of said first epi semiconductor material and a portion of said second epi semiconductor material, said initial fin structure having an axial length; forming a layer of insulating material so as to over-fill said trenches; with said layer of insulating material over-filling said trenches, performing a heating process to form a nanowire structure that is positioned between and spaced apart from said second epi semiconductor material portion and said semiconductor substrate portion of said initial fin structure, wherein said nanowire structure extends for the entire axial length of said initial fin structure and wherein said second epi semiconductor material constitutes the final fin structure of said FinFET device; after forming said nanowire structure, performing a first recess etching process to recess an upper surface of said layer of insulating material such that a portion, but not all, of said final fin structure is exposed; forming a gate structure above and around the exposed portion of said final fin structure; after forming said gate structure, performing a second recess etching process to further recess the previously recessed upper surface of said layer of insulating material such that said nanowire structure is exposed; with said gate structure remaining in position, performing at least one nanowire etching process to remove said nanowire structure and thereby define an under-fin cavity under said final fin structure; and substantially filling said under-fin cavity with a stressed material.