DDR 2D Vref training

摘要

A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

主权项

1. A method, comprising:
performing at least one memory operation following at least one enable operation indicative of performing a double data rate (DDR) memory reference voltage training in a voltage domain by a memory controller; and determining a DDR memory reference voltage based at least upon the performed at least one memory operation.