发明名称 |
Semiconductor chip including a spare bump and stacked package having the same |
摘要 |
A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing. |
申请公布号 |
US9214451(B2) |
申请公布日期 |
2015.12.15 |
申请号 |
US201414179842 |
申请日期 |
2014.02.13 |
申请人 |
Sk Hynix Inc. |
发明人 |
Lee Sang Eun;Kim Chang Il |
分类号 |
H01L25/00;H01L25/065;G11C29/02;H01L23/00;G11C29/44 |
主分类号 |
H01L25/00 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A semiconductor chip, comprising:
a semiconductor substrate; a circuit layer formed over the semiconductor substrate; a bump formed over the circuit layer; a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump; a through electrode configured to pass through the semiconductor substrate on a same line as the bump and electrically couple with the bump or the spare bump in response to a selection signal; a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically couple with the spare bump or the bump in response to the selection signal; a selection signal storage part configured for providing the selection signal; and a memory configured to store information on a fail bump, wherein the selection signal storage part sets the selection signals based on the stored fail bump information. |
地址 |
Gyeonggi-do KR |