发明名称 Integrating multi-output power converters having vertically stacked semiconductor chips
摘要 A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).
申请公布号 US9214415(B2) 申请公布日期 2015.12.15
申请号 US201414181966 申请日期 2014.02.17
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Denison Marie;Carpenter Brian Ashley;Lopez Osvaldo Jorge;Herbsommer Juan Alejandro;Noquil Jonathan
分类号 H01L23/495;H01L23/00;H01L23/498 主分类号 H01L23/495
代理机构 代理人 Shaw Steven A.;Brill Charles A.;Cimino Frank D.
主权项 1. An electronic multi-output device comprising: a substrate including a pad and pins; a composite first chip having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface, and the patterned second and third terminals are on the opposite chip surface; the common first terminal attached to the substrate pad, and the second terminals connected by discrete first and second metal clips to respective substrate pins; a second chip with a third transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the second chip with its first terminal vertically attached to the first clip; and a third chip with a fourth transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the third chip with its first terminal vertically attached to the second clip; and the second and third chips having their second terminals connected by a common clip to a substrate pin.
地址 Dallas TX US