| 摘要 |
PURPOSE:To fetch an output frequency having a channel interval of a fraction of an optical integer of a reference frequency by executing the switching to a requested channel interval by shifting slightly the frequency of a reference oscillator. CONSTITUTION:A titled synthesizer is provided with not only a PLL circuit but also a channel controller 7 for decoding a channel designating signal 21, a D/A converter 8 and a voltage control reference oscillator 11. In this circuit constitution, when a frequency dividing number of a variable frequency divider 6, frequency of the oscillator, an input frequency of a phase detector 3, and a synthesizer output frequency are denoted as Nv, fR (a frequency dividing number of a fixed frequency divider 2 is Ns), fr, and fout, respectively, fr=fR/Ns= fout/Nv is formed in a phase synchronizing state. Accordingly, by setting optionally the frequency divider 6, for instance, a synthesizer of a 100KHz step is obtained. However, switching of a 25kHz step cannot be executed in this state, therefore, in order to enable the 24KHz step, the oscillation frequency of the oscillator 11 is shifted slightly. |
