| 摘要 |
A pixel structure includes a first conductive layer, a semiconductor layer, an insulating layer, a second conductive layer, a passivation layer, and a first electrode layer. The first conductive layer includes a scan line and a bottom electrode. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the insulating layer and includes a top electrode, a first gate, a first source, a first drain, and a data line connected with the first source. The bottom electrode and the top electrode overlap to form a capacitor. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers. |
| 主权项 |
1. A pixel structure comprising:
a first conductive layer comprising a scan line and a bottom electrode; a semiconductor layer comprising a first semiconductor pattern, wherein the first semiconductor pattern has a first channel region, a first source region, and a first drain region; a first insulating layer disposed between the first conductive layer and the semiconductor layer; a second insulating layer disposed on the semiconductor layer; a second conductive layer disposed on the second insulating layer, wherein the second conductive layer comprises a top electrode, a first gate, a first source, a first drain, and a data line connected to the first source, wherein the bottom electrode and the top electrode overlap to form a capacitor; a passivation layer covering the first conductive layer, the semiconductor layer, and the second conductive layer, wherein the passivation layer has a first opening, a second opening, and a third opening, the first opening exposes the first source and the first source region of the semiconductor layer, the second opening exposes the first drain and the first drain region of the semiconductor layer, and the third opening exposes the first gate and the scan line; and a first electrode layer disposed on the passivation layer, wherein the first electrode layer fills into the first opening, the second opening, and the third opening, such that the first source and the first source region are electrically connected to each other, the first drain and the first drain region are electrically connected to each other, and the first gate and the scan line are electrically connected to each other. |
