发明名称 Information processing apparatus with debugging unit and debugging method therefor
摘要 An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.
申请公布号 US9213615(B2) 申请公布日期 2015.12.15
申请号 US201514625814 申请日期 2015.02.19
申请人 Renesas Electronics Corporation 发明人 Matsukawa Kazuya
分类号 G06F11/00;G06F11/26;G06F13/38;G06F13/42;G06F11/28;G06F11/22;G06F11/36;G06F11/273 主分类号 G06F11/00
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A microcontroller comprising: a CPU section configured to execute a program as a debugging target in response to a first clock signal having a clock rate that is variable, wherein the clock rate of said first clock signal is changed in response to an instruction from said CPU section; a first transmitting section configured to output debugging data in response to said first clock signal; a second transmitting section configured to output the debugging data in response to a second clock signal, which is different from said first clock signal and has a clock rate that is fixed.
地址 Kanagawa JP