发明名称 Simulation based system and method for gate oxide reliability enhancement
摘要 A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis. Embodiments may modify the netlist and/or the test stimulus to increase the percentage of stressed circuit components, including bypassing voltage regulators and adding test connections.
申请公布号 US9213787(B1) 申请公布日期 2015.12.15
申请号 US201414231506 申请日期 2014.03.31
申请人 Cadence Design Systems, Inc. 发明人 O'Donovan Richard J.;O'Riordan Donald J.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Kenyon & Kenyon LLP 代理人 Kenyon & Kenyon LLP
主权项 1. A computer-implemented method for improving circuit reliability in circuit design so as to facilitate provision of a manufacturable description of a circuit, the method comprising: inputting a test stimulus, a stress test criterion, and a circuit schematic, to a computer-implemented circuit simulator; using the circuit simulator, simulating the circuit schematic; during the simulating, determining whether at least one circuit component is stressed by exposure to simulated conditions meeting the stress test criterion; modifying at least one of the circuit schematic and the test stimulus to increase the percentage of stressed circuit components, wherein modifying the circuit schematic comprises at least one of selectively bypassing voltage regulators and adding test connections; and tangibly outputting simulation results, in order to provide the manufacturable description of the circuit.
地址 San Jose CA US