Via structure for three-dimensional circuit integration

摘要

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

主权项

1. A method for implementing three-dimensional integration (3Di) of functional components of a circuit comprising:
forming landing pads of upper and lower layers such that each of the landing pads includes a respective protective coating and such that a thickness of each protective coating is greater than the protective coating of any landing pad disposed on a lower layer in a stack and smaller than the protective layer of any landing pad disposed on a higher layer in the stack; aligning an upper layer over an adjacent, lower layer during bonding of the upper and lower layers such that a landing pad disposed on the upper layer is offset from a landing pad disposed on the lower layer; etching through the upper and lower layers to form a via hole in the layers and to expose the landing pads; and filling the via hole with a conductive material to form a via that couples the landing pads of the upper and lower layers.