| 摘要 |
Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections. |
| 主权项 |
1. A semiconductor device, comprising:
N (N is an integer equal to two or more) number of address lines; N number of data lines; and a plurality of storage sections, each of the storage sections including:
an address decoder which decodes an address inputted from the N number of address lines, and outputs a word selection signal to a word line; anda plurality of storage elements, each of which being connected to the word line and the data lines, storing data configuring a truth table, and inputting and outputting the data to and from the data lines based on the word selection signal inputted from the word line, wherein the N number of address lines of one storage section are respectively connected to the data lines of the N number of other storage sections, and the N number of data lines of one storage section are respectively connected to the address lines of the N number of other storage sections, wherein the address decoder includes a row decoder and a column decoder, wherein the row decoder decodes an address inputted from the M (M is an integer equal to five or less) number of address lines, and outputs the word selection signal to the word line, and wherein the column decoder decodes an address inputted from the L (L is an integer of N−5) number of address lines and outputs a data selection signal which selects the N number of data lines outputted from the plurality of storage elements. |
