发明名称 VARIABLE DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a load variation of a power circuit 1 on each cycle basis.SOLUTION: A variable delay circuit includes: a delay stage in which delay units are connected in cascade; a compensation stage, having the same configuration as the delay stage, to which a signal delayed in the delay stage is input; a power circuit 1 which supplies power to each delay unit in the delay stage and the compensation stage; and a control circuit 21 which controls each switch in the delay stage and the compensation stage. The control circuit 21 controls each switch to make constant the total sum of load capacity which is set to be a connection state at the output terminal of a non-inverted buffer in the delay stage and the compensation stage.
申请公布号 JP2015222851(A) 申请公布日期 2015.12.10
申请号 JP20140105965 申请日期 2014.05.22
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NAKAMURA MITSUO;SHIBATA SHINTARO
分类号 H03K5/131 主分类号 H03K5/131
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