发明名称 |
CLOCK DATA RECOVERY CIRCUIT AND A METHOD OF OPERATING THE SAME |
摘要 |
A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes. |
申请公布号 |
US2015358024(A1) |
申请公布日期 |
2015.12.10 |
申请号 |
US201514716106 |
申请日期 |
2015.05.19 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM Tae Jin;Baek Chang Hoon;Lee Sang Kyu;Lee Jae Youl |
分类号 |
H03L7/08;H03L7/187;H03L7/091;H03L7/099;H03L7/089;H03L7/093 |
主分类号 |
H03L7/08 |
代理机构 |
|
代理人 |
|
主权项 |
1. A clock data recovery circuit, comprising:
a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes. |
地址 |
Gyeonggi-do KR |