发明名称 DYNAMIC CACHE ALLOCATION POLICY ADAPTATION IN A DATA PROCESSING APPARATUS
摘要 A data processing apparatus and method of processing data are disclosed according to which a processor unit is configured to issue write access requests for memory which are buffered and handled by a memory access buffer. A cache unit is configured, in dependence on an allocation policy defined for the cache unit, to cache accessed data items. Memory transactions are constrained to be carried out so that all of a predetermined range of memory addresses within which one or more memory addresses specified by the buffered write access requests lie must be written by the corresponding write operation. If the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses, and the cache unit is configured to operate with a no-write allocate policy, the data processing apparatus is configured to cause the cache unit to subsequently operate with a write allocate policy.
申请公布号 US2015356019(A1) 申请公布日期 2015.12.10
申请号 US201514702049 申请日期 2015.05.01
申请人 ARM LIMITED 发明人 JOHAR Kauser;PENTON Antony John;HUGHES Zemian
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A data processing apparatus comprising: a processor unit configured to issue a write access request which specifies a memory address and a data item in order to cause the data item to be stored in a memory at the memory address; a cache unit configured, in dependence on an allocation policy defined for the cache unit, to store a local copy of an accessed data item from the memory for subsequent access by the processor unit; and a memory access buffer configured to buffer one or more write access requests issued by the processor unit until a memory transaction trigger condition is satisfied and then to cause a memory transaction with respect to the memory to be initiated which comprises carrying out the one or more buffered write access requests, wherein the memory transaction is constrained to carry out a write operation in which all of a predetermined range of memory addresses within which one or more memory addresses specified by the one or more buffered write access requests lies are written by the write operation, wherein the data processing apparatus is configured to identify an access undersize condition when the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses, and when the cache unit is configured to operate with the allocation policy as a no-write allocate policy according to which the local copy of the accessed data item is not stored in the cache unit and the access undersize condition is met, the data processing apparatus is configured to cause the cache unit to subsequently operate with the allocation policy as a write allocate policy according to which the local copy of the accessed data item is stored in the cache unit.
地址 Cambridge GB
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