| 摘要 |
The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. |
| 主权项 |
1. A method for producing a semiconductor device, comprising:
a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; after the first step, a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate constituted by a first polysilicon, a second pillar-shaped semiconductor layer, and a second dummy gate constituted by a first polysilicon; after the second step, a third step of forming a third dummy gate and a fourth dummy gate on side walls of the first dummy gate, the first pillar-shaped semiconductor layer, the second dummy gate, and the second pillar-shaped semiconductor layer; after the third step, a fourth step of forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer, a lower portion of the first pillar-shaped semiconductor layer, and a lower portion of the second pillar-shaped semiconductor layer; after the fourth step, a fifth step of depositing an interlayer insulating film, exposing upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, removing the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, forming a gate insulating film around the first pillar-shaped semiconductor layer and the second pillar-shaped semiconductor layer, removing a portion of the gate insulating film located in a periphery of a bottom portion of the second pillar-shaped semiconductor layer, depositing a first metal, exposing an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer, forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer, and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; after the fifth step, a sixth step of depositing a second gate insulating film around the first pillar-shaped semiconductor layer, on the gate electrode and the gate line, around the second pillar-shaped semiconductor layer, and on the contact electrode and the contact line, depositing a second metal, exposing an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the second pillar-shaped semiconductor layer, removing a portion of the second gate insulating film on the first pillar-shaped semiconductor layer, depositing a third metal, and etching portions of the third metal and the second metal to form a first contact in which the second metal surrounds an upper side wall of the first pillar-shaped semiconductor layer and a second contact which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer; and after the sixth step, a seventh step of depositing a second interlayer insulating film, forming a contact hole, depositing a fourth metal and a nitride film, removing portions of the fourth metal and the nitride film on the second interlayer insulating film to form a pillar-shaped nitride film layer and a lower electrode in the contact hole, the lower electrode surrounding a bottom portion of the pillar-shaped nitride film layer and the pillar-shaped nitride film layer, etching back the second interlayer insulating film to expose an upper portion of the lower electrode that surrounds the pillar-shaped nitride film layer, removing the exposed upper portion of the lower electrode that surrounds the pillar-shaped nitride film layer, depositing a resistance-changing film so that the resistance-changing film surrounds the pillar-shaped nitride film layer and is connected to the lower electrode, etching the resistance-changing film to make the resistance-changing film remain as a side wall on an upper portion of the pillar-shaped nitride film layer, forming a reset gate insulating film so that the reset gate insulating film surrounds the resistance-changing film, and forming a reset gate. |
