| 摘要 |
A method for manufacturing a semiconductor device is provided to increase a contact volume between a gate and a bit line and to reduce contact resistance by forming a metal layer of the gate in a reverse-trapezoid shape. A gate dielectric(310) and a poly silicon layer(320) are formed in turn on a semiconductor substrate(300). The poly silicon layer and the gate dielectric are etched as a gate shape to form a layered pattern. A buffer layer(BO) is formed on the resultant structure to cover the layered pattern. A CMP process is performed on the buffer layer until the layered pattern is exposed. A mold dielectric(MN) is formed on the whole surface of the resultant structure. A gate forming region of the mold dielectric is etched to form a reverse-trapezoid trench exposing the layered pattern. A metal layer(330) is formed to gap-fill the trench. A hard mask layer(340) is formed on the metal layer. The hard mask layer, the metal layer, the mold dielectric, and the buffer layer are etched to have a width greater than the layered pattern and to form a gate(350). The gate has the layered pattern and a reverse-trapezoid metal layer. Spacers(360) are formed on both sidewalls of the gate. An interlayer dielectric is formed on the resultant structure to cover the gate including the spacer. A metal wire is formed on the interlayer dielectric to be contacted to the reverse-trapezoid metal layer.
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