发明名称 PHASE LOCKED LOOP CIRCUIT EQUIPPED WITH UNITY GAIN BANDWIDTH ADJUSTMENT
摘要 An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors.
申请公布号 US2015358025(A1) 申请公布日期 2015.12.10
申请号 US201514734820 申请日期 2015.06.09
申请人 STMicroelectronics International N.V. 发明人 Katyal Amit
分类号 H03L7/10;H03L7/099;H03L7/085 主分类号 H03L7/10
代理机构 代理人
主权项 1. An electronic circuit comprising: a digital phase locked loop; a measurement stage that includes a frequency-to-current converter, the measurement stage configured to measure and adjust a gain of the phase locked loop; and a current comparator that triggers operation of the measurement stage.
地址 Schiphol NL