SEMICONDUCTOR DEVICE AND STRUCTURE

摘要

A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

主权项

1. A 3D device, comprising:
a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection; a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
wherein said first layer comprises a first clock distribution structure,wherein said second layer comprises a second clock distribution structure,wherein said second clock distribution structure is connected to said first clock distribution structure with a plurality of through layer vias, andwherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.