DYNAMICALLY ADJUSTING THE HARDWARE STREAM PREFETCHER PREFETCH AHEAD DISTANCE

摘要

An apparatus for prefetching data for a processor is presented. The apparatus may include a memory, a first counter, a second counter, and a control circuit. The memory may include a table with at least one entry in which the at least one entry may include an expected address of a next memory access and a next address from which to fetch data, wherein the next address is an offset value different from the expected address. The at least one entry may also include a maximum limit for the offset value. The first counter may increment responsive to an address of a memory access matching the expected address. The second counter may increment responsive to the address of the memory access resulting in a cache miss. The control circuitry may be configured to increment the maximum value of the offset value dependent upon a value of the second counter.

主权项

1. An apparatus, comprising:
a memory configured to store a first table, wherein the first table includes a first entry, wherein the first entry includes:
an expected address of a next memory request by a processor;a next address, wherein the next address is greater than or less than the expected address by an offset value; anda maximum limit of the offset value; a first counter configured to increment responsive to a determination that an address of a memory request by the processor matches the expected address; a second counter configured to increment responsive to a determination that the address of the memory request resulted in a cache miss; and a control circuit configured to increment the maximum limit of the offset value dependent upon a value of the second counter.