发明名称 |
LAYOUT DESIGN FOR MANUFACTURING A MEMORY CELL |
摘要 |
A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern. The second interconnection layout pattern overlaps the isolation region. |
申请公布号 |
US2015357279(A1) |
申请公布日期 |
2015.12.10 |
申请号 |
US201414300703 |
申请日期 |
2014.06.10 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
FUJIWARA Hidehiro;LIN Kao-Cheng;LEE Ming-Yi;CHEN Yen-Huei;LIAO Hung-Jen |
分类号 |
H01L23/528;H01L27/092;H01L27/11;H01L29/49;G06F17/50;H01L23/532 |
主分类号 |
H01L23/528 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Hsinchu TW |