发明名称 積層型素子およびその製造方法
摘要 A multilayer inductor device in which parasitic inductance is made smaller while preventing increase in a mounting area of the device and complexity of a wiring pattern, and a manufacturing method of the stated multilayer inductor device. An outer electrode and a terminal electrode are connected to each other through a via hole. A side surface of a non-magnetic member forms a part of an end surface of the device, while the other side surface thereof being in contact with the via hole. A side surface of the via hole that makes contact with the non-magnetic member is opened, which prevents the parasitic inductance from being increased. The via hole being provided in an arbitrary position makes it possible to prevent the wiring pattern from being complicated and a mounting area of the device from being increased.
申请公布号 JP5831633(B2) 申请公布日期 2015.12.09
申请号 JP20140516622 申请日期 2012.10.25
申请人 株式会社村田製作所 发明人 横山 智哉;南條 純一
分类号 H01F17/00;H01F27/29;H01F41/04 主分类号 H01F17/00
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