发明名称 電力増幅回路
摘要 <p>Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor.</p>
申请公布号 JP5828420(B2) 申请公布日期 2015.12.09
申请号 JP20140516816 申请日期 2013.05.21
申请人 株式会社村田製作所 发明人 伊藤 雅広;竹中 幹一郎;田中 聡;松本 秀俊
分类号 H03F1/02;H03F1/32;H03F3/24;H03F3/68 主分类号 H03F1/02
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