发明名称 CDR回路、受信回路、及び、電子装置
摘要 An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.
申请公布号 JP5831225(B2) 申请公布日期 2015.12.09
申请号 JP20110289873 申请日期 2011.12.28
申请人 富士通株式会社 发明人 柴▲崎▼ 崇之
分类号 H04L7/033;H03L7/00 主分类号 H04L7/033
代理机构 代理人
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