Quad flat no-lead (QFN) packaging structure and method for manufacturing the same

摘要

A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.

主权项

1. A method for manufacturing a quad flat no-lead (QFN) packaging structure, the method comprising:
a) providing a metal substrate; b) forming a first photoresist film on a top surface of the metal substrate; c) forming a plating pattern in the first photoresist film using photolithography; d) forming a first metal layer containing a plurality of inner leads by a multi-layer electrical plating process using the plating pattern in the first photoresist film as a mask, such that a lead pitch of the plurality of inner leads is significantly reduced; e) attaching a die in a predetermined region on the top surface of the metal substrate; f) connecting the die and the plurality of inner leads using metal wires by a wire bonding process; g) sealing the die, the plurality of inner leads, and the metal wires with a molding compound; h) etching the metal substrate from a back surface of the metal substrate to form an outer die pad, corresponding to the predetermined area mounted with the die, and a plurality of I/O pads corresponding to the plurality of inner leads; and i) forming a second metal layer on a back surface of the plurality of I/O pads and the outer die pad.